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64 Mbit SPI Serial Dual I/O Flash
SST25VF064C
SST25VF032B32Mb Serial Peripheral Interface (SPI) flash memory
Data Sheet
FEATURES:
* Single Voltage Read and Write Operations - 2.7-3.6V * Serial Interface Architecture - SPI Compatible: Mode 0 and Mode 3 * Dual Input/Output Support - Fast-Read Dual-Output Instruction - Fast-Read Dual I/O Instruction * High Speed Clock Frequency - 80 MHz for High-Speed Read (0BH) - 75 MHz for Fast-Read Dual-Output (3BH) - 50 MHz for Fast-Read Dual I/O (BBH) - 33 MHz for Read Instruction (03H) * Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption - Active Read Current: 12 mA (typical @ 80 MHz) for single-bit read) - Active Read Current: 14 mA (typical @ 75MHz) for dual-bit read) - Standby Current: 5 A (typical) * Flexible Erase Capability - Uniform 4 KByte sectors - Uniform 32 KByte overlay blocks - Uniform 64 KByte overlay blocks * Fast Erase - Chip-Erase Time: 35 ms (typical) - Sector-/Block-Erase Time: 18 ms (typical) * Page-Program - 256 Bytes per page - Single and Dual Input support - Fast Page-Program time in 1.5 ms (typical) * End-of-Write Detection - Software polling the BUSY bit in Status Register * Write Protection (WP#) - Enables/Disables the Lock-Down function of the status register * Software Write Protection - Write protection through Block-Protection bits in status register * Security ID - One-Time Programmable (OTP) 256 bit, Secure ID - 64 bit Unique, Factory Pre-Programmed identifier - 192 bit User-Programmable * Temperature Range - Commercial = 0C to +70C - Industrial: -40C to +85C * Packages Available - 16-lead SOIC (300 mils) - 8-contact WSON (6mm x 8mm) - 8-lead SOIC (200 mils) * All devices are RoHS compliant
PRODUCT DESCRIPTION
The SST 25 series Serial Flash family features a four-wire, SPI-compatible interface that allows for a low pin-count package which occupies less board space and ultimately lowers total system costs. SST25VF064C SPI serial flash memory is manufactured with SST proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST25VF064C significantly improves performance and reliability, while lowering power consumption. The device writes (Program or Erase) with a single power supply of 2.7-3.6V. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies. The SST25VF064C device is offered in 16-lead SOIC (300 mils), 8-contact WSON (6mm x 8mm), and 8-lead SOIC (200 mils) packages. See Figure 2 for pin assignments.
(c)2010 Silicon Storage Technology, Inc. S71392-04-000 04/10 1
The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet
Address Buffers and Latches
X - Decoder
SuperFlash Memory
Y - Decoder
Control Logic
Page Buffer, I/O Buffers and Data Latches
Serial Interface
CE#
SCK
SI/SIO0
SO/SIO1
WP#
RST#/HOLD#
1392 B1.0
FIGURE 1: Functional Block Diagram
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64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet
PIN DESCRIPTION
RST#/HOLD# VDD NC NC NC NC CE# SO/SIO1 Top View
SCK SI/SIO0 NC NC NC NC VSS WP#
CE# SO/SIO1 WP# VSS
1 2 3 4
8 7 6 5
VDD RST#/HOLD# SCK SI/SIO0
Top View
1392 8-WSON P1.0
CE#
1392 16-SOIC P1.0
1 2 3 4
8
VDD RST#/HOLD# SCK SI
SO WP# VSS
Top View
7 6 5
1392 8-soic S3A P1.0
FIGURE 2: Pin Assignments for 16-Lead SOIC, 8-Contact WSON, and 8-Lead SOIC TABLE 1: Pin Description
Symbol SCK Pin Name Serial Clock Functions To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. To transfer commands, addresses, or data serially into the device. Inputs are latched on the rising edge of the serial clock. To transfer data serially out of the device. Data is shifted out on the falling edge of the serial clock. To transfer commands, addresses, or data serially into the device, or data out of the device. Inputs are latched on the rising edge of the serial clock. Data is shifted out on the falling edge of the serial clock. These pins are for Dual I/O mode. The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of any command sequence. The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register. To reset the operation of the device and the internal logic. The device powers on with RST# pin functionality as default. To temporarily stop serial communication with SPI Flash memory while device is selected. This is selected by an instruction sequence. See "Reset/Hold Mode" page 5 for details. To provide power supply voltage: 2.7-3.6V
T1.0 1392
SI SO SIO[0:1]
Serial Data Input Serial Data Output Serial Data Input/ Output for Dual I/O Mode
CE# WP# RST#/HOLD#
Chip Enable Write Protect Reset Hold
VDD VSS
Power Supply Ground
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64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet
MEMORY ORGANIZATION
The SST25VF064C SuperFlash memory array is organized in uniform 4 KByte erasable sectors with 32 KByte overlay blocks and 64 KByte overlay erasable blocks. The SST25VF064C supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal.
DEVICE OPERATION
The SST25VF064C is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol. The SPI bus consists of four control lines; Chip Enable (CE#) is used to select the device, and data is accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK).
CE#
MODE 3 MODE 3 MODE 0
SCK SI SO
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
DON'T CARE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
1392 F04.0
HIGH IMPEDANCE
FIGURE 3: SPI Protocol
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64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet
Reset/Hold Mode
The RST#/HOLD# pin provides either a hardware reset or a hold pin. From power-on, the RST#/HOLD# pin defaults as a hardware reset pin (RST#). The Hold mode for this pin is a user selected option where an EHLD instruction enables the Hold mode. Once selected as a hold pin (HOLD#), the RST#/HOLD# pin will be configured as a HOLD# pin, and goes back to RST# pin only after a poweroff and power-on sequence. Reset If the RST#/HOLD# pin is used as a reset pin, RST# pin provides a hardware method for resetting the device. Driving the RST# pin high puts the device in normal operating mode. The RST# pin must be driven low for a minimum of TRST time to reset the device. The SO pin is in high impedance state while the device is in reset. A successful reset will reset the status register to its power-up state (BPL, BUSY and WEL = 0; BP3, BP2, BP1, and BP0 = 1). See Table 2 for default power-up modes. A device reset during an active Program or Erase operation aborts the operation and data of the targeted address range may be corrupted or lost due to the aborted erase or program operation.
CE# TRECR TRECP TRECE SCK TRST RST# TRHZ SO
SI
1292 F28.0
FIGURE 4: Reset Timing Diagram TABLE 2: Reset Timing Parameters
Symbol TRST TRHZ TRECR TRECP TRECE Parameter Reset Pulse Width Reset to High-Z Output Reset Recovery from Read Reset Recovery from Program Reset Recovery from Erase Min 100 105 100 10 1 Max Units ns ns ns s ms
T2.1392
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64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet
Hold Operation
The EHLD instruction enables the hold pin functionality of the RST#/HOLD# pin. Once converted to a hold pin, the RST#/HOLD# pin functions as a hold pin until the device is powered off and on. After the power cycle, the pin functionality returns as a reset pin (RST#) after the power on. The HOLD# pin is used to pause a serial sequence using the SPI flash memory, but without resetting the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD# mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal. The HOLD mode ends when the HOLD# signal's rising edge coincides with the SCK active low state. If the falling edge of the HOLD# signal does not coincide with the SCK active low state, then the device enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the HOLD# signal does not coincide with the SCK active low state, then the device exits from Hold mode when the SCK next reaches the active low state. See Figure 5 for Hold Condition waveform. Once the device enters Hold mode, SO will be in highimpedance state while SI and SCK can be VIL or VIH. If CE# is driven high during a Hold condition, the device returns to Standby mode. As long as HOLD# signal is low, the memory remains in the Hold condition. To resume communication with the device, HOLD# must be driven active high, and CE# must be driven active low. See Figure 5 for Hold timing.
SCK
HOLD# Active Hold Active Hold Active
1392 F05.0
FIGURE 5: Hold Condition Waveform
Write Protection
SST25VF064C provides software Write protection. The Write Protect pin (WP#) enables or disables the lock-down function of the status register. The Block-Protection bits (BP3, BP2, BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 5 for the Block-Protection description. Write Protect Pin (WP#) The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register. When WP# is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined by the value of the BPL bit (see Table 3). When WP# is high, the lock-down function of the BPL bit is disabled. TABLE 3: Conditions to execute Write-StatusRegister (WRSR) Instruction
WP# L L H BPL 1 0 X Execute WRSR Instruction Not Allowed Allowed Allowed
T3.0 1392
Security ID
SST25VF064C offers a 256-bit Security ID (Sec ID) feature. The Security ID space is divided into two parts - one factory-programmed, 64-bit segment and one user-programmable 192-bit segment. The factory-programmed segment is programmed at SST with a unique number and cannot be changed. The user-programmable segment is left unprogrammed for the customer to program as desired. Use the Program SID command to program the Security ID using the address shown in Table 7. Once programmed, the Security ID can be locked using the Lockout SID command. This prevents any future write to the Security ID. The factory-programmed portion of the Security ID can never be programmed, and none of the Security ID can be erased.
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64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet
Status Register
The software status register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the Memory Write protection. During an internal Erase or TABLE 4: Status Register
Bit 0 1 2 3 4 5 6 Name BUSY WEL BP0 BP1 BP2 BP3 SEC1 Function 1 = Internal Write operation is in progress 0 = No internal Write operation is in progress 1 = Device is memory Write enabled 0 = Device is not memory Write enabled Indicate current level of block write protection (See Table 5) Indicate current level of block write protection (See Table 5) Indicate current level of block write protection (See Table 5) Indicate current level of block write protection (See Table 5) Security ID status 1 = Security ID space locked 0 = Security ID space not locked 1 = BP3, BP2, BP1, BP0 are read-only bits 0 = BP3, BP2, BP1, BP0 are readable/writable Default at Power-up 0 0 1 1 1 1 01 Read/Write R R R/W R/W R/W R/W R
Program operation, the status register may be read only to determine the completion of an operation in progress. Table 4 describes the function of each bit in the software status register.
7
BPL
0
R/W
T4.0 1392
1. The Security ID status will always be `1' at power-up after a successful execution of the Lockout SID instruction; otherwise, the default at power up is `0'.
Busy The Busy bit determines whether there is an internal Erase or Program operation in progress. A `1' for the Busy bit indicates the device is busy with an operation in progress. A `0' indicates the device is ready for the next valid operation. Write Enable Latch (WEL) The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If the Write-Enable-Latch bit is set to `1', it indicates the device is Write enabled. If the bit is set to `0' (reset), it indicates the device is not Write enabled and does not accept any memory Write (Program/ Erase) commands. The Write-Enable-Latch bit is automatically reset under the following conditions: * * * * * * * * * * Power-up Write-Disable (WRDI) instruction completion Write-Status Register instruction completion Page-Program instruction completion Dual-Input Page-Program instruction completion Sector-Erase instruction completion Block-Erase instruction completion Chip-Erase instruction completion Program SID instruction completion Lockout SID instruction completion
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64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet Block Protection (BP3,BP2, BP1, BP0) The Block-Protection (BP3, BP2, BP1, BP0) bits define the size of the memory area, as shown in Table 5, to be software protected against any memory Write (Program or Erase) operation. The Write-Status-Register (WRSR) instruction is used to program the BP3, BP2, BP1 and BP0 bits as long as WP# is high or the Block-Protect-Lock (BPL) bit is 0. Chip-Erase can only be executed if BlockProtection bits are all 0. After power-up, BP3, BP2, BP1 and BP0 are set to the defaults specified in Table 5. Block Protection Lock-Down (BPL) WP# pin driven low (VIL), enables the Block-ProtectionLock-Down (BPL) bit. When BPL is set to 1, it prevents any further alteration of the BPL, BP3, BP2, BP1, and BP0 bits. When the WP# pin is driven high (VIH), the BPL bit has no effect and its value is "Don't Care". After power-up, the BPL bit is reset to 0. Security ID Status (SEC) The Security ID Status (SEC) bit indicates when the Security ID space is locked to prevent a Write command. The SEC is `1' after the host issues a Lockout SID command. Once the host issues a Lockout SID command, the SEC bit can never be reset to `0.'
TABLE 5: Software Status Register Block Protection FOR SST25VF064C
Status Register Bit1 Protection Level None Upper 1/128 Upper 1/64 Upper 1/32 Upper 1/16 Upper 1/8 Upper 1/4 Upper 1/2 All Blocks All Blocks All Blocks All Blocks All Blocks All Blocks All Blocks All Blocks BP3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BP2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BP1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BP0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Protected Memory Address 64 Mbit None 7F0000H-7FFFFFH 7E0000H-7FFFFFH 7C0000H-7FFFFFH 780000H-7FFFFFH 700000H-7FFFFFH 600000H-7FFFFFH 400000H-7FFFFFH 000000H-7FFFFFH 000000H-7FFFFFH 000000H-7FFFFFH 000000H-7FFFFFH 000000H-7FFFFFH 000000H-7FFFFFH 000000H-7FFFFFH 000000H-7FFFFFH
T5.0 1392
1. Default at power-up for BP3, BP2, BP1, and BP0 is `1111'. (All Blocks Protected)
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64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet
INSTRUCTIONS
Instructions are used to read, write (Erase and Program), and configure the SST25VF064C. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. The Write-Enable (WREN) instruction must be executed prior any Page-Program, Dual-Input Page-Program, Sector-Erase, Block-Erase, Write-Status-Register, Chip-Erase, Program SID, or Lockout SID instructions. The complete list of instructions is provided in Table 6. All instructions are synchronized off a high to low transition of CE#. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. CE# must be driven TABLE 6: Device Operation Instructions
Instruction Read Fast-Read Dual I/O Fast-Read Dual-Output High-Speed Read Sector-Erase4 32 KByte Block-Erase5 64 KByte Block-Erase6 Chip-Erase Page-Program Dual-Input PageProgram RDSR7 EWSR WRSR WREN WRDI RDID8 JEDEC-ID EHLD Read SID Program SID9 Lockout SID9
1. 2. 3. 4.
low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for Read, Read-ID, and Read-Status-Register instructions). Any low to high transition on CE#, before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to standby mode. Instruction commands (Op Code), addresses, and data are all input from the most significant bit (MSB) first.
Description Read Memory Read Memory with Dual Address Input and Data Output Read Memory with Dual Output Read Memory at Higher Speed Erase 4 KByte of memory array Erase 32KByte block of memory array Erase 64 KByte block of memory array Erase Full Memory Array To Program 1 to 256 Data Bytes To Program 1 to 256 Data Bytes Read-Status-Register Enable-Write-Status-Register Write-Status-Register Write-Enable Write-Disable Read-ID JEDEC ID Read Enable HOLD# pin functionality of the RST#/ HOLD# pin Read Security ID Program User Security ID area Lockout Security ID Programming
Op Code Cycle1 0000 0011b (03H) 1011 1011b (BBH) 0011 1011b (3BH) 0000 1011b (0BH) 0010 0000b (20H) 0101 0010b (52H) 1101 1000b (D8H) 0110 0000b (60H) or 1100 0111b (C7H) 0000 0010b (02H) 1010 0010b (A2H) 0000 0101b (05H) 0101 0000b (50H) 0000 0001b (01H) 0000 0110b (06H) 0000 0100b (04H) 1001 0000b (90H) or 1010 1011b (ABH) 1001 1111b (9FH) 1010 1010b (AAH) 1000 1000b (88H) 1010 0101b (A5H) 1000 0101b (85H)
Address Cycle(s)2 3 33 3 3 3 3 3 0 3 3 0 0 0 0 0 3 0 0 1 1 0
Dummy Cycle(s) 0 13 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Data Cycle(s) 1 to 1 to 3 1 to 3 1 to 0 0 0 0 1 to 256 1 to 1283 1 to 0 1 0 0 1 to 3 to 0 1 to 32 1 to 24 0
T6.0 1392
One bus cycle is eight clock periods. Address bits above the most significant bit can be either VIL or VIH. One bus cycle is four clock periods (dual operation) 4KByte Sector Erase addresses: use AMS-A12, remaining addresses are don't care but must be set either at VIL or VIH.
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64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet
5. 6. 7. 8. 32KByte Block Erase addresses: use AMS-A15, remaining addresses are don't care but must be set either at VIL or VIH. 64KByte Block Erase addresses: use AMS-A16, remaining addresses are don't care but must be set either at VIL or VIH. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#. Manufacturer's ID is read with A0 = 0, and Device ID is read with A0 = 1. All other address bits are 00H. The Manufacturer's ID and device ID output stream is continuous until terminated by a low-to-high transition on CE#. 9. Requires a prior WREN command.
Read (33 MHz)
The Read instruction, 03H, supports up to 33 MHz Read. The device outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE#. The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space. For example, once the data from address location 7FFFFFH has been read, the next output will be from address location 000000H. The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits A23-A0. CE# must remain active low for the duration of the Read cycle. See Figure 6 for the Read sequence.
CE#
MODE 3
012345678
15 16
23 24
31 32
39 40
47
48
55 56
63 64
70
SCK
MODE 0
SI MSB SO
03
ADD. MSB HIGH IMPEDANCE
ADD.
ADD. N DOUT MSB
1392 F06.0
N+1 DOUT
N+2 DOUT
N+3 DOUT
N+4 DOUT
FIGURE 6: Read Sequence
High-Speed Read (80 MHz)
The High-Speed Read instruction supporting up to 80 MHz Read is initiated by executing an 8-bit command, 0BH, followed by address bits A23-A0 and a dummy byte. CE# must remain active low for the duration of the High-Speed Read cycle. See Figure 7 for the High-Speed Read sequence. Following a dummy cycle, the High-Speed Read instruction outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE#. The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wraparound) of the address space. For example, once the data from address location 7FFFFFH is read, the next output is from address location 000000H.
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64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet
CE#
MODE 3
012345678
15 16
23 24
31 32
39 40
47 48
55 56
63 64
71 72
80
SCK
MODE 0
SI SO
0B
ADD.
ADD.
ADD.
X N
DOUT
HIGH IMPEDANCE
N+1
DOUT
N+2
DOUT
N+3
DOUT
N+4
DOUT
1392 F07.0
MSB
FIGURE 7: High-Speed Read Sequence
Fast-Read Dual-Output (75 MHz)
The Fast-Read Dual-Output (3BH) instruction outputs data up to 75 MHz from the SIO0 and SIO1 pins. To initiate the instruction, execute an 8-bit command (3BH) followed by address bits A23-A0 and a dummy byte on SI/SIO0. Following a dummy cycle, the Fast-Read Dual-Output instruction outputs the data starting from the specified address location on the SIO1 and SIO0 lines. SIO1 outputs, per clock sequence, odd data bits D7, D5, D3, and D1; and SIO0 outputs even data bits D6, D4, D2, and D0. CE# must remain active low for the duration of the Fast-Read DualOutput instruction cycle. See Figure 8 for the Fast-Read Dual-Output sequence. The data output stream is continuous through all addresses until terminated by a low-to-high transition on CE#. The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer automatically increments to the beginning (wraparound) of the address space. for 64 Mbit density, once the data from address location 7FFFFFH has been read the next output will be from address location 000000H.
CE#
MODE 3
012345678
15 16
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCK
MODE 0
24-Bit Address SIO0
3B
Dummy Cycle ADD.
X
IO, Switches from Input to Output
6420642064206420
ADD.
ADD.
DOUT SIO1 HIGH IMPEDANCE
7531 MSB
DOUT
7531 MSB
DOUT
7531 MSB
DOUT
7531 MSB
N
N+1
N+2
N+3
1392 F08.1
FIGURE 8: Fast-Read Dual Output Sequence
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64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet
Fast-Read Dual I/O (50 MHz)
The Fast-Read Dual I/O (BBH) instruction reduces the total number of input clock cycles, which results in faster data access. The device is first selected by driving Chip Enable CE# low. Fast-Read Dual I/O is initiated by executing an 8bit command (BBH) on SI/SIO0, thereafter, the device accepts address bits A23-A0 and a dummy byte on SI/ SIO0 and SO/SIO1. It offers the capability to input address bits A23-A0 at a rate of two bits per clock. Odd address bits A23 through A1 are input on SIO1 and even address bits A22 through A0 are input on SIO0, alternately For example the most significant bit is input first followed by A23/22, A21/ A20, and so on. Each bit is latched at the same rising edge of the Serial Clock (SCK). The input data during the dummy clocks is "don't care". However, the SIO0 and SIO1 pin must be in high-impedance prior to the falling edge of the first data output clock. Following a dummy cycle, the Fast-Read Dual I/O instruction outputs the data starting from the specified address location on the SIO1 and SIO0 lines. SIO1 outputs, per clock sequence, odd data bits D7, D5, D3, and D1; and SIO0 outputs even data bits D6, D4, D2, and D0 per clock edge. CE# must remain active low for the duration of the Fast-Read Dual I/O instruction cycle. The data output stream is continuous through all addresses until terminated by a low-to-high transition on CE#. The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer automatically increments to the beginning (wraparound) of the address space. For example, once the data from address location 7FFFFFH is read, the next output is from address location 000000H. See Figure 9 for the Fast-Read Dual I/o sequence.
CE#
MODE 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK
MODE 0
Dummy Cycle SIO0
BB 642064206420 X
IO, Switches from Input to Output
64206420642064206
DOUT SIO1
7531 7531 7531 X 7531
DOUT
7531
DOUT
7531
DOUT
75317
MSB A23-16 A15-8 A7-0 N
MSB N+1
MSB N+2
MSB N+3
1392 F29.0
FIGURE 9: Fast-Read Dual I/O Sequence
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64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet
Page-Program
The page-Program instruction programs up to 256 bytes of data in the memory. The selected page address must be in the erased state (FFH) before initiating the Page-Program operation. A Page-Program applied to a protected memory area will be ignored. Prior to the program operation, the Write-Enabled (WREN) instruction must be executed. CE# must remain active low for the duration of the Page-Program instruction. The PageProgram instruction is initiated by executing an 8-bit command, 02H, followed by address bits A23-A0. Following the address, at least one byte is needed for the data input. CE# must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TPP for the completion of the internal self-timed PageProgram operation. See Figure 10 for the Page-Program sequence. For Page-Program, the memory range for SST25VF064C is set in 256 byte page boundaries. The device handles shifting of more than 256 bytes of data by keeping the last 256 bytes of data shifted as the correct data to be programmed. If the target address for the Page-Program instruction is not the beginning of the page boundary (A7A0 are not all zero) and the number of data input exceeds or overlaps the end of the address of the page boundary, the excess data inputs will wrap around and will be programmed at the start of that target page.
CE#
MODE 3
012345678
15 16
23 24
31 32
39
SCK SI
MODE 0
02 MSB
ADD. LSB MSB
ADD.
ADD.
Data Byte 1 LSB
LSB MSB
SO
HIGH IMPEDANCE
CE#
2072 2073 2074 2075 2076 2077 2078 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2079
SCK SI
MSB Data Byte 2 LSB MSB Data Byte 3 LSB MSB Data Byte 256 LSB
SO
HIGH IMPEDANCE
1392 F30.0
FIGURE 10: Page-Program Sequence
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64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet
Dual-Input Page-Program (50 MHz)
Dual-Input Page-Program instruction A2H, doubles the data input transfer of normal Page-Program instruction and supports up to 50MHz. Data to be programmed is entered using two I/O pins, SIO1 and SIO0. Prior to the program operation the Write-Enable (WREN) instruction must be executed. The Dual-Input Page-Program instruction is entered by driving CE# low, followed by the instruction code, A2H, three address bytes, and at least one data byte on serial data inputs SIO1 and SIO0 pins. CE# must be driven low for the entire duration of the sequence. The Dual-Input Page-Program instruction programs up to 256 bytes of data in the memory. The selected page address must be in the erased state (FFH) before initiating the Page-Program operation. A Dual-Input Page-Program applied to a protected memory area will be ignored. CE# must be driven high after the seventh and eight bit of the last data byte has been latched; otherwise, the dual input program instruction is not executed. Once CE# is driven high the instruction is executed and the user may poll the WEL and Busy bit of the software status register or wait TPP for the completion of the internal self-timed PageProgram operation. See Figure 10 for the Dual-Input-PageProgram sequence. For Dual-Input Page-Program, the memory range for the SST25VF064C is set in 256 byte page boundaries. The device handles shifting of more than 256 bytes of data by keeping the last 256 bytes of data shifted as the correct data to be programmed. If the target address for the PageProgram instruction is not the beginning of the page boundary (A7-A0 are not all zero) and the number of data input exceeds or overlaps the end of the address of the page boundary, the excess data inputs will wrap around and will be programmed at the start of that target page.
CE#
1052 1053 1054 1055
MODE 3
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31 32 33 34 35 36 37 28 39 40 41 42 43 44 45 46 47
SCK
MODE 0
24-bit Address (1) SIO0
A2 23 22 21 32106420642064206420 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 7531 6420 Data Byte 256 7531
SIO1
High Impedance
7531
75317531
MSB
MSB
MSB
MSB
MSB
1392 F31.0
FIGURE 11: Dual-Input Page-Program
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64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet
Sector-Erase
The Sector-Erase instruction clears all bits in the selected 4 KByte sector to FFH. A Sector-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of any command sequence. The Sector-Erase instruction is initiated by executing an 8-bit command, 20H, followed by address bits A23-A0. Address bits AMS-A12 (AMS = Most Significant address) are used to determine the sector address (SAX), remaining address bits can be VIL or VIH. CE# must be driven high before the instruction is executed. Poll the Busy bit in the software status register or wait TSE for the completion of the internal self-timed Sector-Erase cycle. See Figure 12 for the Sector-Erase sequence.
CE#
MODE 3
012345678
15 16
23 24
31
SCK
MODE 0
SI
MSB
20
ADD.
MSB
ADD.
ADD.
SO
HIGH IMPEDANCE
1392 F13.0
FIGURE 12: Sector-Erase Sequence
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64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet
32-KByte and 64-KByte Block-Erase
The 32-KByte Block-Erase instruction clears all bits in the selected 32 KByte block to FFH. A Block-Erase instruction applied to a protected memory area will be ignored. The 64-KByte Block-Erase instruction clears all bits in the selected 64 KByte block to FFH. A Block-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of any command sequence. The 32-Kbyte BlockErase instruction is initiated by executing an 8-bit command, 52H, followed by address bits A23-A0. Address bits AMS-A15 (AMS = Most Significant Address) are used to determine block address (BAX), remaining address bits can be VIL or VIH. CE# must be driven high before the instruction is executed. The 64-Kbyte Block-Erase instruction is initiated by executing an 8-bit command D8H, followed by address bits A23-A0. Address bits AMS-A15 are used to determine block address (BAX), remaining address bits can be VIL or VIH. CE# must be driven high before the instruction is executed. Poll the Busy bit in the software status register or wait TBE for the completion of the internal self-timed 32KByte Block-Erase or 64-KByte Block-Erase cycles. See Figure 13 for the 32-KByte Block-Erase sequence and Figure 14 for the 64-KByte Block-Erase sequence.
CE#
MODE 3
012345678
15 16
23 24
31
SCK
MODE 0
SI
MSB
52
ADDR
MSB
ADDR
ADDR
SO
HIGH IMPEDANCE
1392 F32.0
FIGURE 13: 32-KByte Block-Erase Sequence
CE#
MODE 3
012345678
15 16
23 24
31
SCK
MODE 0
SI
MSB
D8
ADDR
MSB
ADDR
ADDR
SO
HIGH IMPEDANCE
1327 F33.0
FIGURE 14: 64-KByte Block-Erase Sequence
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64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet
Chip-Erase
The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence. Initiate the Chip-Erase instruction by executing an 8-bit command, 60H or C7H. CE# must be driven high before the instruction is executed. Poll the Busy bit in the software status register or wait TCE for the completion of the internal self-timed Chip-Erase cycle. See Figure 15 for the Chip-Erase sequence.
CE#
MODE 3
01234567
SCK
MODE 0
SI
MSB
60 or C7 HIGH IMPEDANCE
1392 F16.0
SO
FIGURE 15: Chip-Erase Sequence
Read Security ID
To execute a Read SID operation, the host drives CE# low, sends the Read SID command cycle (88H), one address cycle, and then one dummy cycle. Each cycle is eight bits long, most significant bit first. After the dummy cycle, the device outputs data on the falling edge of the SCK signal, starting from the specified address location. The data output stream is continuous through all SID addresses until terminated by a low-to-high transition on CE#. The internal address pointer automatically increments until the last SID address is reached, then outputs wrap around until CE# goes high.
Program Security ID
The Program SID instruction programs one to 24 bytes of data in the user-programmable, Security ID space. The device ignores a Program SID instruction pointing to an invalid or protected address, see Table 7. Prior to the program operation, execute WREN. To execute a Program SID operation, the host drives CE# low, sends the Program SID command cycle (A5H), one address cycle, the data to be programmed, then drives CE# high. The programmed data must be between 1 to 24 Bytes and in whole Byte increments. To determine the completion of the internal, self-timed Program SID operation, poll the BUSY bit in the software status register, or wait TPSID for the completion of the internal self-timed Program SID operation. TABLE 7: Program Security ID
Program Security ID Pre-Programmed at factory User Programmable Address Range 00H - 07H 08H - 1FH
T7.0 1392
Lockout Security ID
The Lockout SID instruction prevents any future changes to the Security ID. Prior to the Lockout SID operation, the Write-Enable (WREN) instruction must be executed. To execute a Lockout SID, the host drives CE# low, sends the Lockout SID command cycle (85H), then drives CE# high. A cycle is 8 bits long, most significant bit first. The user may poll the BUSY bit in the software status register or waits TPSID for the completion of the Lockout SID operation.
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64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet
Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction allows reading of the status register. The status register may be read at any time even during a Write (Program/Erase) operation. When a Write operation is in progress, the Busy bit may be checked before sending any new commands to assure that
the new commands are properly received by the device. CE# must be driven low before the RDSR instruction is entered and remain low until the status data is read. ReadStatus-Register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE#. See Figure 16 for the RDSR instruction sequence.
CE#
MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SCK SI
MODE 0
05
MSB
SO
HIGH IMPEDANCE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB Status Register Out
1392 F17.0
FIGURE 16: Read-Status-Register (RDSR) Sequence
Write-Enable (WREN)
The Write-Enable (WREN) instruction sets the WriteEnable-Latch bit in the Status Register to `1' allowing Write operations to occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. The WREN instruction may also be used to allow execution of the Write-Status-Register (WRSR) instruction; however, the Write-Enable-Latch bit in the Status Register will be cleared upon the rising edge CE# of the WRSR instruction. CE# must be driven high before the WREN instruction is executed.
CE#
MODE 3
01234567
SCK
MODE 0
SI
MSB
06 HIGH IMPEDANCE
1392 F18.0
SO
FIGURE 17: Write Enable (WREN) Sequence
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64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction resets the WriteEnable-Latch bit to `0,' thereby, preventing any new Write operations. The WRDI instruction will not terminate any program or erase operation in progress. Any program or erase operation in progress will continue after executing the WRDI instruction. CE# must be driven high before the WRDI instruction is executed.
CE#
MODE 3
01234567
SCK
MODE 0
SI
MSB
04 HIGH IMPEDANCE
1392 F19.0
SO
FIGURE 18: Write Disable (WRDI) Sequence
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64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet
Enable-Write-Status-Register (EWSR)
The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR) instruction and opens the status register for alteration. The Write-StatusRegister instruction must be executed immediately after the execution of the Enable-Write-Status-Register instruction. This two-step instruction sequence of the EWSR instruction followed by the WRSR instruction works like software data protection (SDP) command structure which prevents any accidental alteration of the status register values. CE# must be driven low before the EWSR instruction is entered and must be driven high before the EWSR instruction is executed.
Write-Status-Register (WRSR)
The Write-Status-Register instruction writes new values to the BP3, BP2, BP1, BP0, and BPL bits of the status register. CE# must be driven low before the command sequence of the WRSR instruction is entered and driven high before the WRSR instruction is executed. See Figure 19 for EWSR or WREN and WRSR instruction sequences. Executing the Write-Status-Register instruction will be ignored when WP# is low and BPL bit is set to `1'. When the WP# is low, the BPL bit can only be set from `0' to `1' to lock-down the status register, but cannot be reset from `1' to `0'. When WP# is high, the lock-down function of the BPL bit is disabled and the BPL, BP0, BP1, BP2, and BP3 bits in the status register can all be changed. As long as BPL bit is set to `0' or WP# pin is driven high (VIH) prior to the lowto-high transition of the CE# pin at the end of the WRSR instruction, the bits in the status register can all be altered by the WRSR instruction. In this case, a single WRSR instruction can set the BPL bit to `1' to lock down the status register as well as altering the BP0, BP1, BP2, and BP3 bits at the same time. See Table 3 for a summary description of WP# and BPL functions.
CE#
MODE 3
01234567
MODE 3 MODE 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
MODE 0
SI MSB SO
50 or 06 MSB
01 HIGH IMPEDANCE
STATUS REGISTER IN 76543210 MSB
1392 F20.0
FIGURE 19: Enable-Write-Status-Register (EWSR) or Write-Enable (WREN) and Write-Status-Register (WRSR) Sequence
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64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet
Enable-Hold (EHLD)
The 8-bit command, AAH, Enable-Hold instruction enables the HOLD functionality of the RST#/HOLD# pin. CE# must remain active low for the duration of the Enable-Hold instruction sequence. CE# must be driven high before the instruction is executed. See Figure 20 for the Enable-Hold instruction sequence.
CE#
MODE 3
01234567
SCK
MODE 0
SI
MSB
AA HIGH IMPEDANCE
1203 F21.0
SO
FIGURE 20: Enable-Hold Sequence
Read-ID (RDID)
The Read-ID instruction (RDID) identifies the device as SST25VF064C and manufacturer as SST. The device information can be read from executing an 8-bit command, 90H or ABH, followed by address bits A23-A0. Following the Read-ID instruction, the manufacturer's ID is located in address 00000H and the device ID is located in address 00001H. Once the device is in Read-ID mode, the manufacturer's and device ID output data toggles between address 00000H and 00001H until terminated by a low to high transition on CE#. After CE# is driven high, the device is put into standby mode. Refer to Tables 8 and 9 for device identification data.
CE#
MODE 3
012345678
15 16
23 24
31 32
39 40
47 48
55 56
63
SCK
MODE 0
SI
MSB
90 or AB
00
00
ADD1
MSB
SO
HIGH IMPEDANCE
MSB
BF
Device ID
BF
Device ID
HIGH IMPEDANCE
Note: The manufacturer's and device ID output stream is continuous until terminated by a low to high transition on CE#. 1. 00H will output the manfacturer's ID first and 01H will output device ID first before toggling between the two.
1392 F21.0
FIGURE 21: Read-ID Sequence TABLE 8: Product Identification
Address Manufacturer's ID Device ID SST25VF064C 00001H 4BH
T8.0 1392
Data BFH
00000H
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64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet
JEDEC Read-ID
The JEDEC Read-ID instruction identifies the device as SST25VF064C and the manufacturer as SST. The device information can be read from executing the 8-bit command, 9FH. Following the JEDEC Read-ID instruction, the 8-bit manufacturer's ID, BFH, is output from the device. After that, a 24-bit device ID is shifted out on the SO pin. Byte 1, BFH, identifies the manufacturer as SST. Byte 2, 25H, identifies the memory type as SPI Serial Flash. Byte 3, 4BH, identifies the device as SST25VF064C. The instruction sequence is shown in Figure 22. The JEDEC Read ID instruction is terminated by a low to high transition on CE# at any time during data output.
CE#
MODE 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCK
MODE 0
SI
9F
SO
HIGH IMPEDANCE
MSB
BF
MSB
25
4B
1392 F22.0
FIGURE 22: JEDEC Read-ID Sequence TABLE 9: JEDEC Read-ID Data
Manufacturer's ID Byte1 BFH Byte 2 25H Device ID Memory Type Memory Capacity Byte 3 4BH
T9.0 1392
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64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet
ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability. Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Package Power Dissipation Capability (TA = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C for 10 seconds Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Output shorted for no more than one second. No more than one output shorted at a time.
Operating Range
Range Commercial Industrial Ambient Temp 0C to +70C -40C to +85C VDD 2.7-3.6V 2.7-3.6V
AC Conditions of Test
Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF See Figure 28
TABLE 10: DC Operating Characteristics (VDD = 2.7-3.6V)
Limits Symbol IDDR IDDR2 IDDR3 IDDW ISB1 ILI ILO VIL VIH VOL VOH Parameter Read Current High-Speed Read Current Fast-Read Dual-Output/Dual I/O Current Program and Erase Current Standby Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VDD-0.2 0.7 VDD 0.2 Min Max 12 25 25 25 20 1 1 0.8 Units mA mA mA mA A A A V V V V Test Conditions CE# = 0.1 VDD/0.9 VDD@33 MHz, SO = open CE# = 0.1 VDD/0.9 VDD@80 MHz, SO = open CE# = 0.1 VDD/0.9 VDD@75/50 MHz CE# = VDD CE# = VDD, VIN = VDD or VSS VIN = GND to VDD, VDD = VDD Max VOUT = GND to VDD, VDD = VDD Max VDD = VDD Min VDD = VDD Max IOL = 100 A, VDD = VDD Min IOH = -100 A, VDD = VDD Min
T10.0 1392
TABLE 11: Capacitance (TA = 25C, f = 1 Mhz, other pins open)
Parameter COUT CIN1
1
Description Output Pin Capacitance Input Capacitance
Test Condition VOUT = 0V VIN = 0V
Maximum 12 pF 6 pF
T11.0 1392
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
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64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet TABLE 12: Reliability Characteristics
Symbol NEND1 TDR
1
Parameter Endurance Data Retention Latch Up
Minimum Specification 10,000 100 100 + IDD
Units Cycles Years mA
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78
T12.0 1392
ILTH1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 13: AC Operating Characteristics
33 MHz Symbol FCLK
1
50 MHz Min 9 9 0.1 0.1 5 5 5 5 50 7 7 0 3 5 5 5 5 5 7 7 7 7 0 Max 50
75/80 MHz Min 6 6 0.1 0.1 5 5 5 5 50 7 0 2 4 5 5 5 5 7 7 0 6 25 25 50 2.5 1.0 Max 75/80 Units MHz ns ns V/ns V/ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms ms ms
T13.1 1392
Parameter Serial Clock Frequency High-Speed Read Serial Clock High Time Serial Clock Low Time Serial Clock Rise Time (Slew Rate) Serial Clock Fall Time (Slew Rate) CE# Active Setup Time CE# Active Hold Time CE# Not Active Setup Time CE# Not Active Hold Time CE# High Time CE# High to High-Z Output SCK Low to Low-Z Output Data In Setup Time Data In Hold Time HOLD# Low Setup Time HOLD# High Setup Time HOLD# Low Hold Time HOLD# High Hold Time HOLD# Low to High-Z Output HOLD# High to Low-Z Output Output Hold from SCK Change Output Valid from SCK Sector-Erase Block-Erase Chip-Erase Page-Program Program Security ID
Min 13 13 0.1 0.1 5 5 5 5 50 0 3 5 5 5 5 5
Max 33
TSCKH TSCKL TSCKR2 TSCKF TCES3 TCEH
3
TCHS3 TCHH TCPH TCHZ TCLZ TDS TDH THLS THHS THLH THHH THZ4 TLZ4 TOH TV TSE TBE TSCE TPP TPSID
4 3
0 15 25 25 50 2.5 1.0
10 25 25 50 2.5 1.0
1. Maximum clock frequency for Read Instruction, 03H, is 33 MHz Maximum clock frequency Fast-Read Dual-Output (3BH) is 75 MHz Maximum clock frequency Fast-Read Dual I/O (BBH) is 50 MHz Maximum clock frequency for High-Speed Read, OBH, is 80 MHz Maximum clock frequency for Dual-Input Page-Program, A2H, is 50 Mhz 2. Maximum Rise and Fall time may be limited by TSCKH and TSCKL requirements 3. Relative to SCK. 4. Not 100% tested in production.
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64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet
TCPH CE# TCHH SCK TDS TDH TSCKR TSCKF LSB HIGH-Z
1392 F23.0
TCES
TCEH
TCHS
SI
MSB HIGH-Z
SO
FIGURE 23: Serial Input Timing Diagram
CE# TSCKH SCK TCLZ SO TV SI
1392 F24.0
TSCKL
TOH MSB LSB
TCHZ
FIGURE 24: Serial Output Timing Diagram
CE# THHH SCK THLH THZ SO SI HOLD#
1392 F25.0
THLS
THHS
TLZ
FIGURE 25: Hold Timing Diagram
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64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet
Power-Up Specifications
All functionalities and DC specifications are specified for a VDD ramp rate of greater than 1V per 100 ms (0V to 3V in less than 300 ms). If the VDD ramp rate is slower than 1V/100 ms, a hardware reset is required. The recommended VDD power-up to RESET# high time should be greater than 100 s to ensure a proper reset. See Table 14 and Figures 26 and 27 for more information. TABLE 14: Recommended System Power-up Timings
Symbol TPU-READ1 TPU-WRITE1 Parameter VDD Min to Read Operation VDD Min to Write Operation Minimum 100 100 Units s s
T14.0 1392
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TPU-READ VDD 0V RESET# VIH VDD min
TRECR CE#
1203 F37.0
Note: See Table 2 on page 5 for TRECR parameter.
FIGURE 26: Power-Up Reset Diagram
VDD VDD Max Chip selection is not allowed. All commands are rejected by the device.
VDD Min TPU-READ TPU-WRITE
Device fully accessible
Time
1392 F26.0
FIGURE 27: Power-up Timing Diagram
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64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet
VIHT VHT
INPUT REFERENCE POINTS
VHT
OUTPUT
VLT VILT
VLT
1392 F37.0
AC test inputs are driven at VIHT (0.9VDD) for a logic "1" and VILT (0.1VDD) for a logic "0". Measurement reference points for inputs and outputs are VHT (0.6VDD) and VLT (0.4VDD). Input rise and fall times (10% 90%) are <5 ns.
Note: VHT - VHIGH Test VLT - VLOW Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test
FIGURE 28: AC Input/Output Reference Waveforms
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64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet
PRODUCT ORDERING INFORMATION
SST 25 XX VF XX 064 C XXX X 80 XX - 4I - XX SC E XX X Environmental Attribute E1 = non-Pb Package Modifier C = 16 leads A = 8 contacts Package Type S = SOIC (300 mil body width) Q2 = WSON (6mm x 8mm) S3 = SOIC (200 mil body width) Temperature Range C = Commercial = 0C to +70C I = Industrial = -40C to +85C Minimum Endurance 4 = 10,000 cycles Operating Frequency 80 = 80 MHz Version C = Page-Program Device Density 064 = 64 Mbit Voltage V = 2.7-3.6V Product Series 25 = Serial Peripheral Interface flash memory
1. Environmental suffix "E" denotes non-Pb solder. SST non-Pb solder devices are "RoHS Compliant".
Valid combinations for SST25VF064C SST25VF064C-80-4I-SCE SST25VF064C-80-4I-S3AE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
SST25VF064C-80-4I-Q2AE
SST25VF064C-80-4C-Q2AE
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64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet
PACKAGING DIAGRAMS
7.40 7.60
10.00 10.65
Pin #1 Identifier
10.08 10.50 7 4 places 2.35 2.65 .33 .51 .10 .30 .23 .32 .38 1.27 .020x45 7 4 places
1.27 BSC
Note:
1. Complies with JEDEC publication 95 MS-013 AA dimensions (except as noted), although some dimensions may be more stringent. = JEDEC min is 10.10; SST min (10.08) is less stringent = JEDEC min is 0.40; SST min (0.38) is less stringent 2. All linear dimensions are in metric (min/max). 3. Coplanarity: 0.1 (.05) mm. 4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.
16.soic-SC-ILL.3
FIGURE 29: 16-Lead Plastic Small Outline Integrated Circuit (SOIC) SST Package Code SC
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64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet
TOP VIEW
8.00 0.10 Pin #1
SIDE VIEW
0.2
BOTTOM VIEW
Pin #1 1.27 BSC 4.8 6.0
A A
6.00 0.10
0.076
0.45 0.35
0.05 Max 0.80 0.70
Note: 1. All linear dimensions are in millimeters (max/min). 2. Untoleranced dimensions are nominal target dimensions. 3. The external paddle is electrically connected to die back-side and VSS. This paddle can be soldered to the PC board; SST suggests connecting this paddle to VSS of the unit. Connection of this paddle to any other voltage potential will result in shorts and/or electrical malfunction of the device.
0.55 0.45
CROSS SECTION
Detail A-A 0.80 0.70
1mm 8-wson-6x8-Q2A-2.0
FIGURE 30: 8-Contact Very-very-thin Small Outline No-lead (WSON) SST Package Code: Q2A
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64 Mbit SPI Serial Dual I/O Flash SST25VF064C
Data Sheet
TOP VIEW
SIDE VIEW
Pin #1 Identifier
0.48 0.35 7.34 7.08 1.27 BSC END VIEW 10 4 places 5.38 5.18 8.10 7.70 0.25 0.05 2.16 1.75 0.25 0.19 0.80 0.50 0 8
Note: 1. All linear dimensions are in millimeters (max/min). 2. Coplanarity: 0.1 mm 3. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads.
1mm
8-soic-5x8-S3A-1.0
FIGURE 31: 8-Lead Small Outline Integrated Circuit (SOIC) SST Package Code S3A
TABLE 15: Revision History
Number 00 01 Description Date Sep 2008 Apr 2009
* * * * * * * *
Initial release of data sheet Added 8-contact WSON Q2A package Added Security ID information throughout Updated Table 6 on page 9 Revised "Fast-Read Dual-Output (75 MHz)" on page 11 and "Fast-Read Dual I/O (50 MHz)" on page 12. Modified Figure 8 on page 11. Updated Table 13 on page 24 Added Commercial temperature range in Features, page 1; Operating Range, page 23; and Product Ordering Information, page 28 Added 8-lead SOIC S3A package Changed Max Value of IDDR2 and IDDW to 25mA in Table 10 on page 23 Revised Table 6 on page 9 Updated address information on page 31.
02 03 04
* * * *
Sep 2009 Dec 2009 Apr 2010
Silicon Storage Technology, Inc. www.SuperFlash.com or www.sst.com
(c)2010 Silicon Storage Technology, Inc. S71392-04-000 04/10
31

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